ANNA UNIVERSITY- COMBATORE
B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009.
ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER
DIGITAL ELECTRONICS
PART-A
Answer all questions. (20*2=40)
1. State De-Morgans theorem.
2. Briefly explain the streamlined method of converting binary to decimal number with example.
3. Give the Gray code for the binary number (111)2.
4. Subtract the following:0101 1011-0000 0101.
5. Draw a 1 to 16 demultiplexer circuit.
6. What is priority encoder.
7. Show the common-cathode type of seven segment indicator.
8. Design a half adder using NAND gates only.
9. Draw the truth table for a NOR gate RS flip flop.
10. Obtain D flip flop from JK flip flop.
11. Differentiate synchronous counter and Asynchronous counter.
12. Draw a modulo 6 counter.hat is saturation delay time? Explain.
13. Compare bipolar family transistors with MOS family transistors.
14. what is race condition? How can it be eliminated?
15. What is essential hazard? Give an example.
16. Compare volatile data storage with non volatile data storage.
17. How is combinational logic generated in FPGA.
18. What is a DRAM? How is it refreshed?
19. Draw a macrocell of PLD.
2. Briefly explain the streamlined method of converting binary to decimal number with example.
3. Give the Gray code for the binary number (111)2.
4. Subtract the following:0101 1011-0000 0101.
5. Draw a 1 to 16 demultiplexer circuit.
6. What is priority encoder.
7. Show the common-cathode type of seven segment indicator.
8. Design a half adder using NAND gates only.
9. Draw the truth table for a NOR gate RS flip flop.
10. Obtain D flip flop from JK flip flop.
11. Differentiate synchronous counter and Asynchronous counter.
12. Draw a modulo 6 counter.hat is saturation delay time? Explain.
13. Compare bipolar family transistors with MOS family transistors.
14. what is race condition? How can it be eliminated?
15. What is essential hazard? Give an example.
16. Compare volatile data storage with non volatile data storage.
17. How is combinational logic generated in FPGA.
18. What is a DRAM? How is it refreshed?
19. Draw a macrocell of PLD.
PART-B
Answer any five. (5*12=60)
Answer any five. (5*12=60)
1. Simplify the following Boolean expression using three variable maps:
a) XY+X'Y'Z'+X'YZ'
b) X'Y'+YZ+X'YZ'
c) X'Y+YZ+Y'Z
2. Design a 3-bit parity generator circuit and the circuit of a 4-bit parity checker using even and odd parity bit.
a) XY+X'Y'Z'+X'YZ'
b) X'Y'+YZ+X'YZ'
c) X'Y+YZ+Y'Z
2. Design a 3-bit parity generator circuit and the circuit of a 4-bit parity checker using even and odd parity bit.
3. Discuss in detail about state reduction problem and state assignment problem.
4. Explain the operation of clocked masterslave JK flipflop and D flipflop with neat digrams.
5. Discuss in brief about the design procedure of an asychronous circuits starting from the statement of the problem and culminates in a logic diagram.
6. Explain with a suitable example the procedure for analyzing a synchronous sequential circuit
with SR latches.
7. Write short notes on :
a) PAL
b) FPGA
a) PAL
b) FPGA
8. Discuss in detail about the types of Read only memories.
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